A foreword

The phase locked loop one kind can make the outcoming signal is on frequency and phase place and synchronous circuit of input signal, namely enter and lock the state or in-step condition systematically And then, the phase difference between outcoming signal and system input signal of the turbonator is zero, or keep as the constant. Traditional phase locked loop each part was imitated circuit implementation, generally include the phase discriminator PD , loop filter LF , voltage controlled oscillator VCO Basic part of three cycles.

With the development of digital technique, the whole digital phase-locked loop ADPLL AllDigital Phase-Locked Loop Develop progressively. What is called complete digital phase-locked loop, it is all digitization of cycle part, adopting digital phase discriminator, digital loop filter, digital controlled oscillator forms the phase locked loop, and the signals in the system are all digital signals. Compared with phase locked loop of the traditional simulation circuit implementation, because of the shortcoming of avoiding the temperature drift of the analog phase-locked loop present and apt to be influenced by voltage change etc., thus possess advantages such as reliability high, having steady operation, conveniently regulable,etc.. Digital phase locking cyclical cycle bandwidth and center frequency are adjustable, apt to construct the high-order phase locked loop in programming, and employ it in the number system, does not need A/ D and D/ A to change. Widely used in all respects such as MODEM modulate-demodulate, frequency synthesis, FM stereosound decoding, image manipulation,etc..

With electronic design automation EDA Technical development, can adopt the large-scale programmable logic device such as CPLD or FPGA And VHDL language comes to design the special purpose chip ASIC and number system. This text has finished the cyclical design of the digital phase locking, and can imbed the overall system SoC, form the phase locked loop on-chip.

2 digital phase locking cyclical architecture and operating principle

74XX297 appears initially, employs the most extensive the whole digital phase-locked loop, design, analyze in order to consult with this chip in this text. ADPLL basic structure is shown as in Fig. 1, is mainly turned into mould forward-backward counter, pulse adding or subtracting the circuit and except that part of the N counter 4 by phase discriminator, K and formed. It is Mfc and 2Nfc respectively that K turns into counter of the mould and pulse and adds or subtracts the clock in the circuit. Here fc is the center frequency of cycle, generally speaking M and N are all the power of integer of 2.

2.1 Phase discriminator

The commonly used phase discriminator has two kinds of types: XOR-gate XOR Phase discriminator and border control the phase discriminator ECPD . The XOR-gate phase discriminator relatively inputs phase difference e between Fin phase place and outcoming signal Fout phase place, and output the error signal Se to turn into counting the direction signal of mould forward-backward counter as K. When the cycle is locked, e =0,Se is a rectangular wave of 50% for a duty ratio. Act as e = / 2 o’clock, Se equals 1; Act as e =- / 2 o’clock, Se equals 0. So the phase discriminator phase difference of XOR-gate is terminal it is / 2, it is that the border controls the phase discriminator phase difference to be terminal.

2.2 K turns into the mould forward-backward counter

K Have turned into the mould forward-backward counter and dispelled the high-frequency composition in the error signal Se that the phase discriminator outputs, guarantee the characteristic of the cycle is steady. It is mainly as the direction pulse according to the output of the phase discriminator that K turns into the mould forward-backward counter, output and add or subtract the pulse signal. When Se is the low level, the counter goes on and adds operation, if the result added reaches the module value preserved, output a carry pulse signal CARRY; When Se is the high level, the counter reduces operation, if the result reduced is up to zero, output a borrow pulse signal BORROW.

2.3 pulses add or subtract the circuit

Receive INC and DEC signal that the pulse added or subtracted the circuit respectively in CARRY and BORROW signal that K turns into the mould forward-backward counter. The pulse adds or subtracts the circuit implementation to inputting number frequency and tracing and adjustment in the phase place, make the outcoming signal lock on frequency and phase place of the input signal finally, can call it the digital controlled oscillator.

2.4 divided by N counter

Except that N counter adds or subtracts the output IDOUT of the circuit and carries on N frequency demultiplication to the pulse, gets the outcoming signals Fout of the whole cycle. Meanwhile, because fc =IDCLOCK/ 2N, so can receive different cycle center frequency fc through changing the value N of the frequency demultiplication.

Cyclical realization and emulation of 3 digital phase locking

Design in the intersection of Altera and the intersection of Max and Plus of Company developing software at the platform originally, utilize VHDL language to use the top-down systematic design method, finish the design of ADPLL. Design the logical circuit of cycle each part separately according to the request of each function module in the system at first, and verify emulation, then combine every part and carry on system simulation and prove.

The XOR-gate phase discriminator and except that the realization of N counter is comparatively simple, no longer explain in detail.

3.1 K turns into the mould forward-backward counter

K Turn into the mould forward-backward counter two independent counters ” UPCOUNTER” ,” DOWN COUNTER” Make up, correspond to q0 in the design, q1 separately. K is for counter module value,power of integer on it is always 2, can from input a [3.. 0]Control change. The operation of the counter is controlled by DN/ UP signal. M time that the clock clk frequency is the digital phase-locked loop center frequency, clk rising edge counts. K counter presets the modulus at first, then regard outcoming signal of the phase discriminator as the direction pulse, control the internal counter to add, reduce and count. If this signal is high, ” DOWN COUNTER” Decrease progressively and calculate effectively, ” UP COUNTER” Keep as zero; On the contrary, ” UP COUNTER” Calculate totalizing effectively, ” DOWN COUNTER” Keep as presetting the modulus. ” UP COUNTER” When counter value exceeds K, increase exports as 1, the clear of counter. ” DOWN COUNTER” Counter value is 0 o’clock, decrease exports as 1, the counter resumes as presetting the modulus.

a[3.. 0]=At 1 o’clock, presume K-value is 4. K turns into the artificial waveform of forward-backward counter of the mould and is shown as in Fig. 2.

3.2 pulses add or subtract the circuit

The pulse adds or subtracts the circuit to need to utilize a plurality of flip-flops to cooperate and produce sequence, its output is IDOUT. When there is no carry or borrow pulse signalling, he carries on the external reference clock two frequency demultiplication; When there are carry pulse signals incing, meddle in half a pulse in two frequency demultiplication signals that are outputted, in order to improve the frequency of the outcoming signal; When there are pulse signals dec of borrowing, deduct half a pulse in two frequency demultiplication signals that are outputted, in order to reduce the frequency of the outcoming signal. VHDL designs codes as follows, Fig. 3 is its artificial waveform.

Cyclical realization and emulation of 3.3 digital phase locking

Join each module of cycle and finish the design of ADPLL. In order to simplify and design, turn K into clock Mclk and pulse of the mould forward-backward counter to add or subtract the circuit clock 2Nclk and connect together, fin is equal to the center frequency fc of cycle, fc =312.5 kHz. Fetch M =16,N =8,Mclk =5 MHz. Act as a [3.. 0]=At 1 o’clock, presume K-value is 4. For observation, turn K into the input signal udcon of the mould forward-backward counter to draw.

The cycle is after entering to lock the state, udcon is that a duty ratio is 50% rectangular wave. Systematic schematic diagram and artificial waveform are differentiated if pursue 4, Fig. 5 is shown.

From The hold-in range theoretical value of getting ADPLL is: F0/ 4, namely 234.375- 390.625 kHz. According to the artificial experimental result, can realize the steady phase-locked frequency domain: 250- 357.14 KHz, is slightly smaller than the theoretical value range.

Setting-up and analysis of 4 the whole digital phase-locked loop mathematical model

Combine simulation and digital phase-locked theoretical anylysis, can get digital phase locking cyclical phase place and transfer function of the phase difference. Fig. 6 is the cyclical mathematical model of the digital phase locking.

The phase discriminator can be regarded as the gain to noise temperature ratio as the module of Kd, output the input DN/ UP that factor k of duty ratio turned into the counter of the mould as K, control ” UP COUNTER” Sum ” DOWN COUNTER” Movement.

As to the XOR-gate phase discriminator, phase difference is equal to / 2 o’clock, k =1,Phase difference is equal to – / 2 o’clock, k =-1. So to the gain to noise temperature ratio Kd of phase discriminator of XOR-gate =2/ , the same can get the border and control the gain to noise temperature ratio Kd of the phase discriminator =1/ .

It is that f0 is the center frequency of the cycle that K turns into the frequency that the counter of the mould produces CARRY signal :

Turn into the counter of the mould as to K, its input/output signal is k and carry respectively, corresponding Laplace transforms to ks And carrys ,So K turns into the phase transfer function of the counter of the mould:

Add or subtract the circuit as to the pulse, because each CARRY pulse makes its output IDOUT increase by 1/ 2 cycles, can regard him as the gain to noise temperature ratio as 1/ 2 of the module. Except that N counter can be regarded as the gain to noise temperature ratio as the module of 1 / N. Phase transfer function Hs of the system Expressed as:

In order to get the minimum ripple, as to the XOR-gate XOR Phase discriminator and border control the phase discriminator ECPD ,K module value is fetched as M/ 4 and M/ 2 separately, corresponding time constants are: EXOR =N/ 8 T0, ECPD =N/ 2 T0, among them T0 =1/ f0. Therefore, it is N the smaller, the shorter the stabilization time of ADPLL is. The phase locked loop designed in this text, Kd =2/ , M =16,N =8,K =M/ 4 =4,Inserting the time constant formula can be had: =T0.

5 concludes the speech

This text introduces a first order ADPLL design method, utilize VHDL language to finish system design and emulation. The module value of forward-backward counter can change at will in ADPLL, the tracing that used for controlling ADPLLs compensates and locking time. Except that the intersection of N and frequency demultiplication of counter worth, can also change at will, make the intersection of ADPLL and all right the intersection of tracing and different input signal of center frequency. The designed ADPLL module can also be regarded as the reusable IP kernel, applies to other designs. Meanwhile, on the basis of theoretical anylysis, set up the cyclical first order mathematical model of digital phase locking, thus can simplify the design of ADPLL according to the concrete quantitative calculating parameter of designing requirement.