In fields such as modern electron measuring, communication system and biomedicine,etc., often involve gathering and storing the data to the analog signal of broadband, so that the computer further carries on data processing. In order to gather the high-speed analog signal undistortedly, pay attention to according to enduring Kui Sri Lankan particularly, sampling frequency must be more than 2 times of the signal frequency, until resistance resist more frequently and orthogonal the intersection of array and digital the intersection of demodulation and law resist, make an uproar performance to the intersection of signal and every decision of counting of sample of cycle in the the intersection of parameter and the intersection of formation of image and technology, sample and count the more, resist and make an uproar the higher performance. When the sampling signal is very tall in frequency, in order to sample more during a cycle the sampling signal, need to improve the frequency of sampling the clock, but can not reach the high-frequency speed required or can’t meet the demands to wait for to store processing speed because of ADC device clock speed of the system we can adopt low The speed ADC device samples and gathers to the analog signal of broadband to make the system easy to realize the data through equivalent time.

An equivalent time samples the principle

Equivalent time it samples technology to be periodicity or accurate periodic high frequency and the signal is transformed to the slow speed signal of low frequency fast. Only circuit to the sample had requirement for high frequency on the circuit, reduced and sampled the signal after varying to deal with, reveal the requirements for speed of the circuit greatly, have simplified the difficulty of design of the whole system. Equivalent time samples and divides sampling (sequential equivalent sampling) for the order , stochastical sampling (random equivalent sampling) And combine the mixing of these two ways to sample (compound equivalent sampling) equivalently . The order in introducing the equivalent time that two kinds of hardwares realize to sample in literature [3 ], [4 ] separately is sampled.

Now the mixed time in I sample the equivalent time of introduction samples, the equivalent time to the periodic signal samples like Fig. 1 (a) Shown.

In cross axle in the first cycle ‘ Time) The second and 6 clock of place rise along sampling about analog signal,say arrowhead at picture whether last moment. Can gather two points during one cycle, and then rise in the clock of the 11th and the 15th place of the second cycle cross axle along sampling the analog signal. In order to make it convenient for and observe and arrange the wave form of the first to the fifth cycle longitudinally here. Can see as from each the intersection of cycle and the intersection of time and getting late one the intersection of clock and cycle of starting point as sampled point of first week second cycle. As from third cycle the intersection of time and getting late one the intersection of clock and cycle of starting point as sampled point of second week third cycle. We can find the second sampled point has already entered the fifth cycle when the fourth cycle sampled. Until five cycle attempt, continue, go on, it samples to be as from the intersection of time and late one the intersection of clock and cycle of starting point as sampled point of the fourth week five cycle by means of the above week we, then the value that we will find the sample starting point in the fifth cycle sampled has repeated the number value sampled in first cycle. So we can stop, sample we get, adopt 8 that reach in one the intersection of sine and wave form of cycle like 6th wave form what sketch map say in the 1 Fig. then at this moment A data are clicked.

Theoretical foundation when can gather a plurality of points in providing equivalent time to sample in the literature [5 ] each cycle, theoretical foundation when can gather the single point in providing equivalent time to sample in the literature [6 ] each cycle.

We had already reached or has been close to meeting the clock requirement of processing speed through the frequency division of paying the high-frequency clock. In Fig. 1 (b) The clock signal minimum in range of China, in order to sample the clock. By Fig. 1 (b) If can very clear, the intersection of clock and the intersection of wave form and along go on and sample to the signal rising in clock after the frequency division, will get like Fig. 1 (a) then The equivalent time that China expresses samples.

The equivalent time of Fig. 1 samples the sketch map

2 equivalent time based on FPGA samples and realizes

2.1 The systematic hardware realizes the block diagram

Overall block diagram such as 2 Fig. of system, whom FPGA control sample clock, connect to the intersection of ADC and clock part of device equivalently, ADC device samples the analog signal of broadband under the control of clock, the data gathered are conveyed to FIFO in FPGA, again until data of FIFO transmit FIFO in the USB, until the intersection of FIFO and data push away, send computer to in the USB USB to in the FPGA FPGA, the computer reconstructs and deals with the data received. As to the acquisition of cycle of signal, the cycle resisting in the resistance more frequently and gathering the signal in the technology of formation of image of parameter is decided by cycle sending a message, and can get to get by adopting to other complicated cycles.

Systematic scheme block diagram of Fig. 2

2.2 The procedure sampling the clock equivalent time realizes

Fig. 3 has shown the input port based on that the equivalent time that FPGA produces samples the module and exported ports. Among them CLK shows the input of the high-frequency clock, what RESET showed is to reset the input terminus, what FREN_CON showed is that frequency division controls input to use for controlling fen of the high-frequency clock frequently, how many high-frequency clock signals wave form is included what SANM_CONT showed is the cycle of the analog signal, what CLK_ADC_OUT showed is to export the clock port, this port is connected to the modulus and changed the device (ADC) Clock import port.

The equivalent time of Fig. 3 samples the module picture

The following realizes equivalent time samples the code of the necessary clock:

SIGNAL SAMP_CONTS: STD_LOGIC_VECTOR ( 11

DOWNTO 0) : =( OTHERS => ’0′) ;

SIGNAL ADC_CLK_BANK: STD_LOGIC_VECTOR ( 11

DOWNTO 0) : =( OTHERS => ’0′) ;

SIGNAL CLK_CNT : INTEGER RANGE 0 TO 5000: =0;

SIGNAL CLK_TANK: STD_LOGIC: =’0′;

SIGNAL EN : STD_LOGIC: =’1′;

BEGIN

PROCESS( CLK, RESET)

BEGIN

IF RESET =’1′ THEN EN< =’1′;

ELSE

IF CLK’EVENT AND CLK =’1′ THEN

IF SAMP_CONTS

SAMP_CONTS< =SAMP_CONTS+’1′;

IF ADC_CLK_BANK

ADC_CLK_BANK< =ADC_CLK_BANK+’1′;

ELSE EN< =’0′;

END IF;

ELSE

ADC_CLK_BANK< =( OTHERS => ’0′) ;

SAMP_CONTS< =( OTHERS => ’0′) ;

EN< =’1′;

END IF;

END IF;

END IF;

END PROCESS;

—The frequency division controls some procedures, use as clock of ADC

PROCESS( CLK, RESET, EN)

BEGIN

IF RESET =’1′ THEN

CLK_TANK< =’0′;

CLK_CNT< =0;

ELSE

IF EN =’1′ THEN

IF CLK’EVENT AND CLK =’1′ THEN

IF ( CLK_CNT =( CONV_INTEGER ( FREN_CON) /2) -1)

THEN

CLK_TANK< =NOT CLK_TANK;

CLK_CNT< =0;

ELSE CLK_CNT< =CLK_CNT+1;

END IF;

END IF;

ELSE

CLK_TANK< =’0′;

CLK_CNT< =0;

END IF;

END IF;

END PROCESS;

CLK_ADC_OUT< =CLK_TANK;

END;

3 wave form emulation

The wave form emulation in Fig. 4 is to equal clock cycle of 8 CLKs in a cycle of the analog signal, CLK_ADC_OUT carry on 4 frequency division to CLK and clock after the frequency division account for empty than 50% for suppose. The clock that the arrowhead points to on the 1st rises along indicating the first cycle is over, rise along entering the second cycle. The same, the rising of the clock that the arrowhead means, along marking the end of the second cycle of the 2nd, rise along indicating that entered the third cycle.

Wave form emulation of Fig. 4

Rise to carry on the frequency division to CLK from the first of CLK at the same time and can get CLK_ADC_OUT clock signal along beginning to time during the first cycle, when rise to turn in the second of CLK along CLK_ADC_OUT level in the first cycle (exist and prolong) ,Rise to turn in the third along CLK_ADC_OUT level during the second cycle, rise to turn in the fourth of CLK along CLK_ADC_OUT level during the third cycle. Find out the artificial picture of the wave form is to Fig. 1 (a, OK? ? , (b) Two charts reach the realization of the clock. Should notice, have 8 rising of CLK too in first cycle along in here, but it show mean one whether CLK be risen until the first CLK clocks risen with second cycle later clock arrowhead along during wave form.

4 conclusions

The equivalent time that this text introduced sampled technology because used FPGA to sample technology, make in looks under one period of cycle in sampling signal than only can gather, sample and improve a lot by one the intersection of order and equivalent time of point on one period of cycle, and can control and is gathered the collection in signal one cycle to count thus can realize the control of frequency conversion is sampled according to the subsequent device processing speed. Realize that samples time equivalently through FPGA, the complexity which the reducing system realizes, can going on to code very convenient fix, enable the systematic debugging further more simple and more convenient at the same time.

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