Characteristic function of 1 MAX1200

New ADC is moving along the road toward low power consumption, high speed, high-resolution, the structure of the new assembly line is exactly the effective method to realize high-speed low power consumption ADC. But MAX1200 adopts this new technical high speed, the representatives of high precision, low power consumption ADC.

MAX1200 is the single scale integration analog-digital converters of a 16, sampling rate reachable 1Msps, CMOS integral circuit of its inside adopts the multiple assembly line structure of the whole differentiating, it has fast digital correction of error and self-alignment function, can guarantee the non- stray dynamic range SFDR with 16′s linear scale and 91dB in the whole sampling rate ,And the good signal to noise ratio SNR And harmonic distortion THD Characteristic. MAX1200 mainly applies to fields such as image system of the high-resolution, scanner, digital communication, measurement instrument and die Datenannahme,etc.; Its main technological characteristic is as follows:

Adopt the single power 5V to supply power;

Adopt difference input, VREF of , positively the intersection of reference voltage and RFPF by external 4. 906V voltage reference is offered, the negative-going reference voltage RFNF is connected to imitate the ground;

When the input signal is 100kHz, its signal to noise ratio is 87dB;

The non- stray dynamic range when the input signal is 100kHz is 91dB;

When 1Msps speed and 5V supply power, its power consumption of device is 273mW;

Have 0. The differentiating of 5LSB is not a linear error;

Adopt the output of the tristate, complement of two’s;

Have fast, controlled self-alignment functions;

Adopt 44 feet MQFP to capsulate, Table 1 is their functional specifications.

2 operating principles

Streamline type pipeline ADC is also called subarea type ADC, it made up of cascade connected circuit of several grades, every include one sample / hold amplifier, one ADC, DAC and a summing circuit of low resolution, among them the summing circuit also includes offering the inter-stage amplifier of the gain to noise temperature ratio. Fast rigorous the intersection of n and the intersection of location and converter its divide for two-section subarea of the above ‘ Assembly line Come to finish. Sample / hold unit of per grade of circuit is come to inputting quantization by the thick A/ D converter of a m location definition first after taking a sample to the input signal, take one at least the intersection of n and the intersection of location and product digital-analogue converter MDAC of precision then To produce one and is correspondent to consequential simulation level of quantization and sent to the summing circuit, then subtract the intersection of simulation and level this in input signal by summing circuit, enlarge accurately difference to, deliver the the intersection of circuit and process to behind the a certain fixed gain. After such treatment at all levels, it is changed the residual signal by more high-accuracy detailed A/ D converter of K location and then. Combine the output of the above-mentioned thick, detailed A/ D at all levels in order to form high-accuracy n location output finally. The ones that should be paid attention to are: The operation must meet the following inequalities in order to correct and overlap the mistake:

l m k> n

Among them, l is the progression, m hits the crude definition of ADC, k, for subdividing the distinguishing rate of meticulous ADC for the units at various levels, but n is the total definition of the assembly line ADC. Schematic diagrams and each grades of internal structure chartses of 4 grades of assembly lines ADC as MAX1200 shown of Fig. 1, among them m =8,l =4,n =16. Because there is mismatching problem between switching capacitors in the switching capacitor assembly line structure adopted, so the precision of the whole circuit is controlled by correcting and normalizing logic. 4 structural sample processes of assembly line are sampled in the input signal and the data output will be introduced for one waiting time between D51- D0, that is to say the assembly line is delayed. But can obtain the serial output in case of continuous sampling. Fig. 2 shows for its sequential chart of data output.

Characteristic function of 1 MAX1200

New ADC is moving along the road toward low power consumption, high speed, high-resolution, the structure of the new assembly line is exactly the effective method to realize high-speed low power consumption ADC. But MAX1200 adopts this new technical high speed, the representatives of high precision, low power consumption ADC.

MAX1200 is the single scale integration analog-digital converters of a 16, sampling rate reachable 1Msps, CMOS integral circuit of its inside adopts the hierarchical assembly line structure of the whole difference, it has fast digital correction of error and self-alignment function, can guarantee the non- stray dynamic range SFDR with 16′s linear scale and 91dB in the whole sampling rate ,And the good signal to noise ratio SNR And harmonic distortion THD Characteristic. MAX1200 mainly applies to fields such as image system of the high-resolution, scanner, digital communication, measurement instrument and die Datenannahme,etc.; Its main technological characteristic is as follows:

Adopt the single power 5V to supply power;

Adopt difference input, VREF of , positively the intersection of reference voltage and RFPF by external 4. 906V voltage reference is offered, the negative-going reference voltage RFNF is connected to imitate the ground;

When the input signal is 100kHz, its signal to noise ratio is 87dB;

The non- stray dynamic range when the input signal is 100kHz is 91dB;

When 1Msps speed and 5V supply power, its power consumption of device is 273mW;

Have 0. The differentiating of 5LSB is not a linear error;

Adopt the output of the tristate, complement of two’s;

Have fast, controlled self-alignment functions;

Adopt 44 feet MQFP to capsulate, Table 1 is their functional specifications.

2 operating principles

Streamline type pipeline ADC is also called subarea type ADC, it made up of cascade connected circuit of several grades, every include one sample / hold amplifier, one ADC, DAC and a summing circuit of low resolution, among them the summing circuit also includes offering the inter-stage amplifier of the gain to noise temperature ratio. Fast rigorous the intersection of n and the intersection of location and converter its divide for two-section subarea of the above ‘ Assembly line Come to finish. Sample / hold unit of per grade of circuit is come to inputting quantization by the thick A/ D converter of a m location definition first after taking a sample to the input signal, take one at least the intersection of n and the intersection of location and product digital-analogue converter MDAC of precision then To produce one and is correspondent to consequential simulation level of quantization and sent to the summing circuit, then subtract the intersection of simulation and level this in input signal by summing circuit, enlarge accurately difference to, deliver the the intersection of circuit and process to behind the a certain fixed gain. After such treatment at all levels, it is changed the residual signal by more high-accuracy detailed A/ D converter of K location and then. Combine the output of the above-mentioned thick, detailed A/ D at all levels in order to form high-accuracy n location output finally. The ones that should be paid attention to are: The operation must meet the following inequalities in order to correct and overlap the mistake:

l m k> n

Among them, l is the progression, m hits the crude definition of ADC, k, for subdividing the distinguishing rate of meticulous ADC for the units at various levels, but n is the total definition of the assembly line ADC. Schematic diagrams and each grades of internal structure chartses of 4 grades of assembly lines ADC as MAX1200 shown of Fig. 1, among them m =8,l =4,n =16. Because there is mismatching problem between switching capacitors in the switching capacitor assembly line structure adopted, so the precision of the whole circuit is controlled by correcting and normalizing logic. 4 structural sample processes of assembly line are sampled in the input signal and the data output will be introduced for one waiting time between D51- D0, that is to say the assembly line is delayed. But can obtain the serial output in case of continuous sampling. Fig. 2 shows for its sequential chart of data output.

Interface circuit of 3 MAX1200 and DSP

U.S.A. TI Company DSP chip TMS320F206 Hereafter referred to as F206 It is a kind of low price, 16 high-performance fixed points DSP, field of can apply to the image manipulation of figure, speech processing, instrument, communication, multimedia and military extensively ing etc.. It operation fast ‘ Reachable 40MIPS ,Strong in function,its source code for ‘ C1x, ‘ C2x compatible,at the same time with ‘ C5x upward compatible, can’t and if you can’t have, close to in TMS320C5x too inside and outside its sheet. Adopt Harvard structure of the procedure separated from data within TMS320F206, it has a specialized hardware multiplier. This chip adopts the pipeline operation of moderate breeze, can offer the special DSP order, and can be fast to realize one kind of treatment algorithms. Fig. 3 is that the peripheral circuit of MAX1200 is connected with interface of TMS320F206.

4 nodules

Can realize the high-speed high-accuracy analog to digital converter with the streamline type ADC, this technology is representatives of new ADC. MAX1200 use with DSP very high speed, it is applied to various digitized systems such as digital communication, high-resolution image system, scanner that the digital acquisition systems of high precision, low power consumption are extensive.