The characteristic that the frequency of radar transmitter of the foundation of this text changes fast, adopt the present new logic control device to study the module of new frequency measurement, the interpolative frequency measurement principle of precision of combining etc., count to the pulse after having a facelift and enlarging directly, realize it to the fast frequency measurement of carrier of single pulse envelope after down-conversion. Have survey accuracy to be high, measure, take short characteristic, can be regarded as the pulse radar monopulse instant frequency measurement module.

A phase shift clock counting method frequency measurement principle

The clock counting method of the phase shift, in order to wait for the frequency measurement law of the precision as the foundation, it is a kind of new interpolative technology, its multi-channel co-frequency but the clock in different phase places is produced by PLL within FPGA, then convey to the corresponding counter and count respectively, turn on every counter of interval of time to count in the real gate at the same time; After the real gate is closed, will add up to the number value to use for frequency measurement and make operation. The concrete method is: The real gate makes and can be carried cnt_ena through the routing of overall clock and count of 4 synchronous counters as the key logic signal Link up, as counting the enabling signal of the counter; The clock signals of No. four, as counting the clock, the clock ends clk of parting and 4 counters of the counter Link up, realize 4 counter count to actual the intersection of gate and pulse width, counter set up as, add, count by 1 in the intersection of clock and rising edge. The counter value of setting up 4 counters is ns1, ns2, ns3, ns4 respectively, suppose the total number value is N’ s, because changes of each counter counter value will make the value of N’ s change, and n21, ns2, ns3, ns4 are correspondent count the clock and have each other 90 degrees of phase difference Tdk/4 count time ,Then counter value N’ s will increase by 1 in every Tdk/4 time. The equivalent carries on frequency multiplication 4 counting the standards of No. one on the clock. After measurement finishes namely the real gate is closed ,Reuse formula computing and receive the measured value of the pulse width of real gate, wait for the frequency measurement formula of the precision:

Compare with formula 1 And 2 Knowing, sum 4 the intersection of counter and the intersection of counter value and ns1, ns2, ns3, ns4 result of operation go on frequency measurement make operation as new counter value, the intersection of frequency measurement and as 4 frequency multiplication of standard frequency equivalent of fruiting its. This conclusion can also explain in terms of relative divergence, because of waiting for the real gate of the frequency measurement law of the precision simultaneously with measured signal, so formula 2 Quantization error that Nx of China does not exist. And real gate and standard clock are out-of-step, then 1′s quantization error that N’ s exists. Then the relative divergence of frequency measurement is:

Because counter value N’ s is nearly 4 times of Ns, so formula 2 The correspondent error is a formula 1 Correspondent 1/4. Namely pass the phase shift clock frequency measurement methods of No. four, in a situation that measurement time and reference clock are constant in frequency, make the metric relative divergence turn into 1/4 of the original error, survey accuracy has been improved by 4 times. If increase the way of the phase shift clock, then survey accuracy will be further improved.

Overall conceptual design of 2 new frequency measurement module

Utilize the intersection of phase shift and the intersection of clock and counting method construct the intersection of intermediate frequency and instant, measure module, come measurement to realize frequency, the measurement target of module of this frequency measurement is the intermediate frequency signal after the radar receiver down-conversion of the pulse. The overall design object is to construct a digitization, totalization, unattended test platform, can meet the requirement for frequency measurement in pulse, can carry on telecommunication, and there are certain transplantation type and staging, set up the basic chassis such as Fig. 1 of the system.

The working mechanism of the overall system is: The operating personnel chooses parameter setting and function to this module through the man-machine interface of the upper computer, the set point of the man-machine interface is transmitted to the one-chip computer through the serial port, the one-chip computer is regarded as the control unit which measures the module, control FPGA to finish the corresponding measurement task, FPGA is responsible for the concrete frequency measurement algorithm to realize. After test is finished, the test result is conveyed to the man-machine interface of the upper computer and revealed through the one-chip computer, the two connect through RS232 serial port. The frequency measurement algorithm circuit within FPGA is the key circuit in the whole design.

3 FPGA frequency measurement algorithm circuit design

It is a key control unit to adopt the StratixII series Model EP2S15F484C5 FPGA of Altera Company. Internal frequency measurement algorithm circuit mainly includes PLL outputs the routing, control unit of sequence, data processing unit of the clock. These units are to realize the algorithmic core of frequency measurement, need to connect every unit interface according to offering each other within FPGA, form intact frequency measurement module, precision frequency measurement function of realizing etc.. Input signals are clock signal of 10 MHz, pulse envelope signal and measured signal; The outcoming signal is counter value of the clock and ns measured signal counter value nx, its total block diagram of principle such as Fig. 2.

Utilize PLL to export multi-channelly and count the clock, can increase one time of frequencies of maximum within FPGA through PLL cascade connected way. Utilize 10 MHz clock frequency multiplication to 50 MHz that EPLL inputs thermostatical Jingzhen at first, transmit it to FPLL as the reference clock of FPLL. Again input clock from frequency multiplication to 400 MHz, phase shift, take a percentage, receive four No. the intersection of phase shift and clock FPLL. The degree of FPLL phase shift is set up as: 0 degrees, 90.0, 180 degrees of, 270.0 degrees, final actual degree keeps the same with arrangement value. Because has assigned 4 overall clock lines around FPLL, so all output clocks of FPLL can carry on the routing of overall clock line through GLOBAL device.

The characteristic that the frequency of radar transmitter of the foundation of this text changes fast, adopt the present new logic control device to study the module of new frequency measurement, the interpolative frequency measurement principle of precision of combining etc., count to the pulse after having a facelift and enlarging directly, realize it to the fast frequency measurement of carrier of single pulse envelope after down-conversion. Have survey accuracy to be high, measure, take short characteristic, can be regarded as the pulse radar monopulse instant frequency measurement module.

A phase shift clock counting method frequency measurement principle

The clock counting method of the phase shift, in order to wait for the frequency measurement law of the precision as the foundation, it is a kind of new interpolative technology, its multi-channel co-frequency but the clock in different phase places is produced by PLL within FPGA, then convey to the corresponding counter and count respectively, turn on every counter of interval of time to count in the real gate at the same time; After the real gate is closed, will add up to the number value to use for frequency measurement and make operation. The concrete method is: The real gate makes and can be carried cnt_ena through the routing of overall clock and count of 4 synchronous counters as the key logic signal Link up, as counting the enabling signal of the counter; The clock signals of No. four, as counting the clock, the clock ends clk of parting and 4 counters of the counter Link up, realize 4 counter count to actual the intersection of gate and pulse width, counter set up as, add, count by 1 in the intersection of clock and rising edge. The counter value of setting up 4 counters is ns1, ns2, ns3, ns4 respectively, suppose the total number value is N’ s, because changes of each counter counter value will make the value of N’ s change, and n21, ns2, ns3, ns4 are correspondent count the clock and have each other 90 degrees of phase difference Tdk/4 count time ,Then counter value N’ s will increase by 1 in every Tdk/4 time. The equivalent carries on frequency multiplication 4 counting the standards of No. one on the clock. After measurement finishes namely the real gate is closed ,Reuse formula computing and receive the measured value of the pulse width of real gate, wait for the frequency measurement formula of the precision:

Compare with formula 1 And 2 Knowing, sum 4 the intersection of counter and the intersection of counter value and ns1, ns2, ns3, ns4 result of operation go on frequency measurement make operation as new counter value, the intersection of frequency measurement and as 4 frequency multiplication of standard frequency equivalent of fruiting its. This conclusion can also explain in terms of relative divergence, because of waiting for the real gate of the frequency measurement law of the precision simultaneously with measured signal, so formula 2 Quantization error that Nx of China does not exist. And real gate and standard clock are out-of-step, then 1′s quantization error that N’ s exists. Then the relative divergence of frequency measurement is:

Because counter value N’ s is nearly 4 times of Ns, so formula 2 The correspondent error is a formula 1 Correspondent 1/4. Namely pass the phase shift clock frequency measurement methods of No. four, in a situation that measurement time and reference clock are constant in frequency, make the metric relative divergence turn into 1/4 of the original error, survey accuracy has been improved by 4 times. If increase the way of the phase shift clock, then survey accuracy will be further improved.

Overall conceptual design of 2 new frequency measurement module

Utilize the intersection of phase shift and the intersection of clock and counting method construct the intersection of intermediate frequency and instant, measure module, come measurement to realize frequency, the measurement target of module of this frequency measurement is the intermediate frequency signal after the radar receiver down-conversion of the pulse. The overall design object is to construct a digitization, totalization, unattended test platform, can meet the requirement for frequency measurement in pulse, can carry on telecommunication, and there are certain transplantation type and staging, set up the basic chassis such as Fig. 1 of the system.

The working mechanism of the overall system is: The operating personnel chooses parameter setting and function to this module through the man-machine interface of the upper computer, the set point of the man-machine interface is transmitted to the one-chip computer through the serial port, the one-chip computer is regarded as the control unit which measures the module, control FPGA to finish the corresponding measurement task, FPGA is responsible for the concrete frequency measurement algorithm to realize. After test is finished, the test result is conveyed to the man-machine interface of the upper computer and revealed through the one-chip computer, the two connect through RS232 serial port. The frequency measurement algorithm circuit within FPGA is the key circuit in the whole design.

3 FPGA frequency measurement algorithm circuit design

It is a key control unit to adopt the StratixII series Model EP2S15F484C5 FPGA of Altera Company. Internal frequency measurement algorithm circuit mainly includes PLL outputs the routing, control unit of sequence, data processing unit of the clock. These units are to realize the algorithmic core of frequency measurement, need to connect every unit interface according to offering each other within FPGA, form intact frequency measurement module, precision frequency measurement function of realizing etc.. Input signals are clock signal of 10 MHz, pulse envelope signal and measured signal; The outcoming signal is counter value of the clock and ns measured signal counter value nx, its total block diagram of principle such as Fig. 2.

Utilize PLL to export multi-channelly and count the clock, can increase one time of frequencies of maximum within FPGA through PLL cascade connected way. Utilize 10 MHz clock frequency multiplication to 50 MHz that EPLL inputs thermostatical Jingzhen at first, transmit it to FPLL as the reference clock of FPLL. Again input clock from frequency multiplication to 400 MHz, phase shift, take a percentage, receive four No. the intersection of phase shift and clock FPLL. The degree of FPLL phase shift is set up as: 0 degrees, 90.0, 180 degrees of, 270.0 degrees, final actual degree keeps the same with arrangement value. Because has assigned 4 overall clock lines around FPLL, so all output clocks of FPLL can carry on the routing of overall clock line through GLOBAL device.

The measured signal is a carrier signal of the pulse modulated wave. Signal this amplifying circuit deal with post forming pulse series, input TCLK pin of FPGA into through have a facelift. Because of the influence of circuit and device, head, range and frequency of the postlude signal of the pulse series are unstable, shown as the frequency fluctuates within FPGA relatively largely, so can only choose the intermediate steady component of the pulse series as measuring the target.The pulse envelope signal is offered by detecting circuit, as the impulse width input signal of the measured signal. If adopt and turn into the frequency measurement way of the gate, the pulse width counter measures the width of each pulse envelope, the value of its pulse width is kept in the negative edge of pulse envelope, and supply the pre- gate counter and count reference value in its prerequisite of rising edge of the next pulse envelope as the pre- gate.

Scheme of this frequency measurement needs to carry on 1 ms measurement of gate time to the continuous wave, as to the standard clock signal of 400 MHz, adopt 20 synchronous counters to count to measured signal and standard clock. Counting the frequency reachable 416 MHz of 20 synchronous counters, the counter value of its maximum is 1048576, count with standard the intersection of clock and the intersection of letter and Guangdong of 400 MHz, correspondent to count time 2.6 ms. Counter transfer the intersection of ALTERA and IP kernel automatic generation that Company offered with the intersection of Quartus6.0 and the intersection of Mega Wizard Plug-in Manager and kit in the software.

4 peripheral circuit design

The peripheral circuit includes offering the thermostatical Jingzhen circuit of the standard 10 MHz clock for FPGA; Amplify, have a facelift the shaping circuit dealt with to the input signal; The intersection of pulse envelope and detection circuit and offer for whole module – 5 V, 1.2 V, 3.3 V, the intersection of 5 V and power supply circuit of voltage.

The frequency measurement accuracy requirement of this subject is 10-6, the frequency accuracy of the Shaker should be up to 10-7 at least, can only choose the voltage-controlled thermostatical crystal oscillator and construct the standard frequency source. The intersection of subject and used Jingzhen this, for products, Company of China, star of Chengdu, until attached the intersection of Allan and the intersection of variance and testing software it gets to be here in second in OCXO inside the instrument 3.3* 10-12, 100 The s one is short and steady in 4.4* 10-12.

Usually there is only one millivolt of order of magnitude in the signal amplitde examined that the video receiver conveys, and the input port of FPGA is generally LVTTL level, so need to input level switch. FPGA LVTTL level that FTOP last 200 MHz,for be able to and the value of this frequency match, do not form the speed bottleneck, adopt ultrafast ECL level to output the comparator ADC-MP563 and finish the signal shaping function, bunch of electricity-linkingup changing device MC100EPT25 finishes the conversion to LVTTL logic level of differentiating ECL level.

The pulse envelope detection circuit measures the envelope curve of the measured signal, is used for measuring impulse width. Adopt the intersection of AD and Company detect the intersection of chip and AD8310 construct detecting circuit, detection in the measured signal adopt the way of importing in single-end. The upper computer constructs the man-machine interface with CV18.0.

5 simulation results explain

Test method: Use the vector signal generator E4438C of Agilent Company and outcoming signal of the arbitrary waveform generator 33250 as the measurand separately, measure its signal frequency with module of this frequency measurement, every counter value is uploaded to the upper computer and dealt with the software through the serial port of the one-chip computer, this software realizes formula 2 through the procedure Algorithm,calculate measuring frequency value. The measuring result is shown in Table 1.

Table 1 is the frequency measurement of the carrier in pulse of indefinite pulse width, gate time is according to measuring and beginning the measured value of the pulse width of the last first pulse envelope to confirm, because E4438C fluctuates while producing 4 s pulse width bigger, so relatively great in some frequency point Time Deviation of real gate. The experiment shows: The pulse modulated wave carrier frequency measurement of system pair, in the indefinite pulse width about 4 s Superior to 10 kHz to the precision of frequency measurement of intermediate frequency under the state.

Table 2 is the frequency measurement of the carrier in pulse of indefinite pulse width. The frequency signal source is the arbitrary waveform generator 33250 of Agilent Company. The experiment shows: The pulse modulated wave carrier frequency measurement of system pair, in the indefinite pulse width less than or equal to 400 ns Superior to 30 kHz to the precision of frequency measurement of intermediate frequency under the state.

6 conclusions

The instant frequency measurement module of precision such as being based on multi-channel phase shift clock that this text puts forward has simple circuit, the high characteristic of the cost performance, it can be used for the frequency measurement in frequency conversion pulse-modulated radar pulse of victory. The circuit of central frequency measurement is totally constructed within FPGA most, the standard clock input is only 10 MHz, not only has reduced the difficulty of routing and plate making, but also the antijamming capability of the module of improvement has guaranteed survey accuracy by a wide margin. The module of whole frequency measurement is realized by a plate card, Pass The Test reaches the desired effect, prove this cipher scheme has very high practicability.