The intersection of frequency and frequency demultiplication at first, produce the intersection of 1HZ and frequency, procedure is as follows:

——————————————————————-

–Comments: The intersection of frequency demultiplication and module, the intersection of reference input and the intersection of frequency and for 1HZ frequency demultiplication

–File: fenpin.vhd

–Author:

–Date: 2012/04/09

–Revise:

–Software: Altera QuartusII 9.0

–Chip: Altera Cyclone FPGA EP1C3T144C8

——————————————————————-

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; –A heavy-duty head file of operator

–The entity describes the part

ENTITY fenpin IS

PORT –Port statement

CLKIN : IN STD_LOGIC;

CLK1HZ : OUT STD_LOGIC

;

END fenpin;

–The structure describes the part

ARCHITECTURE bhv OF fenpin IS

SIGNAL Q : STD_LOGIC;

BEGIN

PROCESSCLKIN –IF sentence put in the process

CONSTANT shuru_05CLK : integer : =50000; –Shuru_05CLK is half of the frequency of reference input, here enables shuru_05CLK=50000,

–Suppose the standard signal is 100000HZ, should be according to inputting the frequency and changing this constant actually

VARIABLE CNT : integer : =0 ;

BEGIN

IF CLKIN’EVENT AND CLKIN =’0′ THEN –Function: The negative edge of clock came at that time, judged the variable CNT =There is not the value of shuru_05CLK

IF CNT =shuru_05CLK THEN — Not equal to continuing totalizing, until CNT =Shuru_05CLK, will believe at this moment

CNT : =0; Q <= NOT Q; — ?Q??,??CNT??,????shuru_05CLK???

ELSE CNT : =CNT 1; –50000Clock once changes, just let Q change once, has reached the frequency demultiplication result.

END IF;

END IF;

END PROCESS; –The process is over

CLK1HZ <= Q ;

END bhv; –Finish the structure

Secondly it is the control module of frequency measurement, mainly used for producing the gate signal of 1S, as follows:

——————————————————————-

–Comments: Control module of frequency measurement

–File: kongzhi.vhd

–Author:

–Date: 2012/04/09

–Revise:

–Software: Altera QuartusII 9.0

–Chip: Altera Cyclone FPGA EP1C3T144C8

——————————————————————-

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

–USE IEEE.STD_LOGIC_UNSIGNED.ALL; –A heavy-duty head file of operator

–The entity describes the part

ENTITY kongzhi IS

PORT –Port statement

CLKK : IN STD_LOGIC;

RST_CNT,CNT_EN,LOAD : OUT STD_LOGIC

;

END kongzhi;

–The structure describes the part

ARCHITECTURE bhv OF kongzhi IS

SIGNAL Q : STD_LOGIC;

BEGIN

PROCESSCLKK –IF sentence put in the process

BEGIN

IF CLKK’EVENT AND CLKK =’1′ THEN

Q <= NOT Q;

END IF;

IF CLKK =’0′ AND Q = ’0′ THENRST_CNT <= '1' ;

ELSE RST_CNT <= '0';

END IF;

END PROCESS; –The process is over

CNT_EN <= Q ;

LOAD <= NOT Q ;

END bhv; –Finish the structure

The third step is a part of counters, treat and examine signals to count the frequency:

——————————————————————-

–Comments: A decade scaler module

–File: CNT10.vhd

–Author:

–Date: 2012/04/09

–Revise:

–Software: Altera QuartusII 9.0

–Chip: Altera Cyclone FPGA EP1C3T144C8

——————————————————————-

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; –A heavy-duty head file of operator

–The entity describes the part

ENTITY CNT10 IS

PORT –Port statement

CLK, CLR, EN, RESET : IN STD_LOGIC;

COUT : OUT STD_LOGIC;

Q : OUT STD_LOGIC_VECTOR 3 DOWNTO 0

;

END CNT10;

–The structure describes the part

ARCHITECTURE bhv OF CNT10 IS

SIGNAL Q1 : STD_LOGIC_VECTOR 3 DOWNTO 0 ; –Define the vector type signal node with wide quad bit

BEGIN

PROCESSCLR,CLK –IF sentence put in the process

BEGIN

IF RESET = ’0′ THEN Q1 <= "0000";COUT <= '0'; –????,?RESET?0???,??????

ELSIF CLR = ’1′ THEN Q1 <= "0000";COUT <= '0'; –????,?CLR?1???,??????

ELSIF CLK’EVENT AND CLK = ’1′ THEN

IF EN =’1′ THEN

IF Q1 <9 THEN Q1 <= Q11;COUT <= '0'; –??????9?????

ELSE Q1 <= "0000";COUT <= '1'; –?????9???,??????

END IF;

END IF;

END IF;

END PROCESS; –The process is over

Q <= Q1; –????

END bhv; –Finish the structure

The intersection of frequency and frequency demultiplication at first, produce the intersection of 1HZ and frequency, procedure is as follows:

——————————————————————-

–Comments: The intersection of frequency demultiplication and module, the intersection of reference input and the intersection of frequency and for 1HZ frequency demultiplication

–File: fenpin.vhd

–Author:

–Date: 2012/04/09

–Revise:

–Software: Altera QuartusII 9.0

–Chip: Altera Cyclone FPGA EP1C3T144C8

——————————————————————-

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; –A heavy-duty head file of operator

–The entity describes the part

ENTITY fenpin IS

PORT –Port statement

CLKIN : IN STD_LOGIC;

CLK1HZ : OUT STD_LOGIC

;

END fenpin;

–The structure describes the part

ARCHITECTURE bhv OF fenpin IS

SIGNAL Q : STD_LOGIC;

BEGIN

PROCESSCLKIN –IF sentence put in the process

CONSTANT shuru_05CLK : integer : =50000; –Shuru_05CLK is half of the frequency of reference input, here enables shuru_05CLK=50000,

–Suppose the standard signal is 100000HZ, should be according to inputting the frequency and changing this constant actually

VARIABLE CNT : integer : =0 ;

BEGIN

IF CLKIN’EVENT AND CLKIN =’0′ THEN –Function: The negative edge of clock came at that time, judged the variable CNT =There is not the value of shuru_05CLK

IF CNT =shuru_05CLK THEN — Not equal to continuing totalizing, until CNT =Shuru_05CLK, will believe at this moment

CNT : =0; Q <= NOT Q; — ?Q??,??CNT??,????shuru_05CLK???

ELSE CNT : =CNT 1; –50000Clock once changes, just let Q change once, has reached the frequency demultiplication result.

END IF;

END IF;

END PROCESS; –The process is over

CLK1HZ <= Q ;

END bhv; –Finish the structure

Secondly it is the control module of frequency measurement, mainly used for producing the gate signal of 1S, as follows:

——————————————————————-

–Comments: Control module of frequency measurement

–File: kongzhi.vhd

–Author:

–Date: 2012/04/09

–Revise:

–Software: Altera QuartusII 9.0

–Chip: Altera Cyclone FPGA EP1C3T144C8

——————————————————————-

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

–USE IEEE.STD_LOGIC_UNSIGNED.ALL; –A heavy-duty head file of operator

–The entity describes the part

ENTITY kongzhi IS

PORT –Port statement

CLKK : IN STD_LOGIC;

RST_CNT,CNT_EN,LOAD : OUT STD_LOGIC

;

END kongzhi;

–The structure describes the part

ARCHITECTURE bhv OF kongzhi IS

SIGNAL Q : STD_LOGIC;

BEGIN

PROCESSCLKK –IF sentence put in the process

BEGIN

IF CLKK’EVENT AND CLKK =’1′ THEN

Q <= NOT Q;

END IF;

IF CLKK =’0′ AND Q = ’0′ THENRST_CNT <= '1' ;

ELSE RST_CNT <= '0';

END IF;

END PROCESS; –The process is over

CNT_EN <= Q ;

LOAD <= NOT Q ;

END bhv; –Finish the structure

The third step is a part of counters, treat and examine signals to count the frequency:

——————————————————————-

–Comments: A decade scaler module

–File: CNT10.vhd

–Author:

–Date: 2012/04/09

–Revise:

–Software: Altera QuartusII 9.0

–Chip: Altera Cyclone FPGA EP1C3T144C8

——————————————————————-

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; –A heavy-duty head file of operator

–The entity describes the part

ENTITY CNT10 IS

PORT –Port statement

CLK, CLR, EN, RESET : IN STD_LOGIC;

COUT : OUT STD_LOGIC;

Q : OUT STD_LOGIC_VECTOR 3 DOWNTO 0

;

END CNT10;

–The structure describes the part

ARCHITECTURE bhv OF CNT10 IS

SIGNAL Q1 : STD_LOGIC_VECTOR 3 DOWNTO 0 ; –Define the vector type signal node with wide quad bit

BEGIN

PROCESSCLR,CLK –IF sentence put in the process

BEGIN

IF RESET = ’0′ THEN Q1 <= "0000";COUT <= '0'; –????,?RESET?0???,??????

ELSIF CLR = ’1′ THEN Q1 <= "0000";COUT <= '0'; –????,?CLR?1???,??????

ELSIF CLK’EVENT AND CLK = ’1′ THEN

IF EN =’1′ THEN

IF Q1 <9 THEN Q1 <= Q11;COUT <= '0'; –??????9?????

ELSE Q1 <= "0000";COUT <= '1'; –?????9???,??????

END IF;

END IF;

END IF;

END PROCESS; –The process is over

Q <= Q1; –????

END bhv; –Finish the structure

The fourth step, latch the frequency measured, namely design the latch:

——————————————————————-

–Comments: Latch module

–File: suocun.vhd

–Author:

–Date: 2012/04/09

–Revise:

–Software: Altera QuartusII 9.0

–Chip: Altera Cyclone FPGA EP1C3T144C8

——————————————————————-

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; –A heavy-duty head file of operator

–The entity describes the part

ENTITY suocun IS

PORT –Port statement

RESET, CLK1HZ : IN STD_LOGIC;

AIN0,AIN1,AIN2,AIN3 : IN STD_LOGIC_VECTOR 3 DOWNTO 0 ;

Q0,Q1,Q2,Q3 : OUT STD_LOGIC_VECTOR 3 DOWNTO 0

;

END suocun;

–The structure describes the part

ARCHITECTURE bhv OF suocun IS

BEGIN

PROCESSCLK1HZ –1HZ input herein is LOAD from control module, LOAD is a signal of 1HZ

VARIABLE T3,T2,T1,T0 : STD_LOGIC_VECTOR 3 DOWNTO 0 ; –Defined variable

BEGIN

IF RESET = ’0′ THEN –The reset signal is effective for low level, act as RESET =0 o’clock, clear of all values

T3 : =” 0000″ ;

T2 : =” 0000″ ;

T1 : =” 0000″ ;

T0 : =” 0000″ ;

ELSIF CLK1HZ’EVENT AND CLK1HZ=’1′ THEN –According to the topic requirement, LOAD rising edge latches the data

T3: =AIN3;

T2: =AIN2;

T1: =AIN1;

T0: =AIN0;

END IF;

Q3 <= T3;

Q2 <= T2;

Q1 <= T1;

Q0 <= T0;

END PROCESS; –The process is over

END bhv; –Finish the structure

It is the decipher that exports revealing in the nixie tube finally:

——————————————————————-

–Comments: The Decoder is designed

–File: decoder.vhd

–Author:

–Date: 2012/04/09

–Revise:

–Software: Altera QuartusII 9.0

–Chip: Altera Cyclone FPGA EP1C3T144C8

——————————————————————-

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY decoder IS

PORT

ain : IN STD_LOGIC_VECTOR 3 DOWNTO 0 ;

yout : OUT STD_LOGIC_VECTOR 6 DOWNTO 0

;

END decoder;

ARCHITECTURE yimaqi OF decoder IS

BEGIN

PROCESS ain

BEGIN

CASE ain IS

WHEN ” 0000″ =